01Overview
Description THE COMPANY
Established in early 2024, at Analogue Insight we are bridging the Analogue and Digital Worlds for Tomorrow through our Chiplet Solutions. Our core expertise lies in developing cutting-edge Chiplet technology that serves as the building block for advanced communication systems. Our Chiplets are designed to offer high performance, scalability, and integration flexibility, enabling our clients to achieve breakthroughs in computation speed, data processing, and connectivity.
For more information about us, check out our website (Analogue Insight) and LinkedIn Page (Analogue Insight: Overview | LinkedIn).
THE ROLE
We are seeking a highly skilled and experienced IC Packaging Engineer to provide technical leadership and architectural ownership of advanced IC and System-in-package(SiP) in a fast-growing startup environment. This role is designed for a senior technologist who combines deep hands-on expertise with system-level thinking, and who thrives in high-ambiguity, high-impact settings.
You will define and drive high-performance, low-power packaging architectures spanning 2D and RDL based fan-out (2.5D), chiplet-based designs, and heterogeneous integration, leading efforts from early technology path finding through production ramp. You will work closely with foundries, OSATs, substrate suppliers, and internal cross-functional teams to shape both product execution and long-term packaging strategy.
Hiring Manager: Christian Borelli, Founder and CSO.
KEY RESPONSIBILITIES
Serve as technical authority for IC and SiP packaging across multiple products and programs. Own package architecture and technology roadmap, aligned with product, cost, and scalability goals. Lead chiplet-based packaging strategies, including UCIe, silicon interposers, 3D stacked die solutions, and advanced RDL. Perform and guide hands-on package design and physical layout, including critical structures for High-speed SerDes/PHY (PCIe, CXL), LPDDR5, UCIe, and Other multi-gigabit interfaces. Define substrate stack-ups, materials, bump/RDL architectures, and DFM guidelines for advanced nodes. Drive SI/PI, thermal, mechanical, and reliability trade-offs at the system and package levels. Lead external engagement with OSATs, foundries, and key suppliers for technology development and manufacturing readiness. Influence product roadmap, risk management, and investment decisions through technical insight. Establish scalable design methodologies, best practices, and reusable packaging flows.
WHAT WERE LOOKING FOR
Must-have Technical skills:
BSEE or MSEE (PhD a plus) in Electrical Engineering, or related field. Minimum of 10+ years of experience with extensive IC packaging expertise for SoCs, ASICs, or memory products. Deep hands-on expertise in Flip-Chip BGA (FCBGA) and System-in-Package (SiP), RDL, silicon interposers, and chiplet architectures (UCIe)Strong understanding of electrical, mechanical, thermal, and reliability design trade-offs, Advanced packaging materials and substrate technologies, Design-for-Manufacturing (DFM) and yield optimizationDemonstrated ability to operate autonomously, make high-impact decisions, and execute in a startup environment. Excellent analytical and problem-solving skills, with a keen eye for detail.Effective communication and teamwork skills, with the ability to collaborate with cross-functional teams.Demonstrated ability to mentor and guide less experienced engineers.Familiarity with industry standards, protocols, and compliance testing.Soft & Professional Skills:
Clear, structured communication in professional Englishable to explain complex results conciselyCollaborative and feedback-oriented mindsetDemonstrated ability to mentor and guide less experienced engineersStrong ownership, reliability, and follow-throughCurious, self-motivated attitude, eager to learn and explore new tools or methodsHigh level of integrity and professionalism in representing the company and handling sensitive information.Cadence Allegro Package Designer (APD) or equivalent EDA tools. Strong background in flip-chip BGA package design and layout. SI/PI expertise preferred, including S-parameter extraction and PDN optimization using HFSS, SIwave, or Ansys Designer. Experience building new packaging methodologies or platforms from scratch.
OUR CULTURE
Were a fully remote team of around 25 people distributed across the UK, Armenia, Italy, the US, Estonia, India, and beyond. We believe great talent is everywhere!
Our values are our north star: We Grow Together, We Win Together. Excellence Builds Relationships. Trust Is Our Currency. Results Matter, but People Create Them.Connected, even remotely: We invest intentionally in staying connected through regular all-hands, 1:1s, technical reviews, and informal coffee chats, so collaboration feels natural and human despite the distance.High ownership, real impact: Everyone contributes directly to customer-facing IP. Your work doesnt disappear into layers of .
