01Responsibilities
- The Candidate will have design responsibility, including floor planning, power grid design, place and route, clock tree synthesis, timing/SI closure, power / EM-IR signoff, physical verification (DRC/LVS/Antenna), and DFM Closure.
- Physical design implementation of state-of-the-art Cadence IPs using Cadence EDA tools - Genus, Innovus, Tempus, Voltus and other backend tools
- Physical design for PPA optimization of performance and power-oriented best-in-class interface IPs such as DDR, LPDDR, PCIE, UCIE, etc and test chips for advanced process nodes, such as 7nm/5nm/3nm/2nm
- An opportunity to work on many varieties of challenging designs, i.e., low power, high-speed and area optimized designs.
- Work closely with RTL design team & Analog Team to ensure on-time, successful tapeouts.
Required skills
- B.Tech/BE/ME/Mtech with 4-6 years hands-on experience in physical design and physical verification.
- Experienced with ASIC design flow, hierarchical physical design strategies, methodologies and understand deep sub-micron technology issues.
- Solid knowledge on physical design, static timing analysis, Low Power Design, EM/IR /crosstalk analysis, formal verification, physical verification, DFM, DFT.
- Successful track records of taping out complex IPs & SoCs at 16/10/7/5/3 nm with different foundries.
- Power user of Cadence implementation tools, such as Genus, Innovus, Quantus, Tempus, PVS, Voltus will be an added advantage
- Automation and programming-minded, coding experience in Makefile/Tcl/Tk/Perl/python assisted with AI.
- Should have excellent communication, analytical and problem-solving skills, should be self-motivated and valuable team player
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