Lead FPGA Design Engineer

Astrome Technologies is looking for a Lead RTL Design Engineer to play a key role in developing innovative 5G ready wireless systems. As a Lead RTL Design Engineer, you will be responsible for defining and implementing RTL architectures, guiding a team of engineers, conducting synthesis, and ensuring system performance optimization.

- Lead the definition and implementation of RTL architectures for wireless baseband systems. - Mentor a team of engineers in the design, verification, and implementation of RTL designs using System Verilog. - Conduct synthesis, implement designs on FPGAs, and resolve timing violations. - Collaborate with Software and Hardware teams to troubleshoot and optimize system performance. - Ensure adherence to design methodologies and best practices throughout the development process.

- 8+ years of experience in RTL design and verification, with a proven track record in leading design teams. - In-depth expertise in digital design principles, RTL design, and FPGA development flows. - Advanced proficiency in HDLs, particularly SystemVerilog/Verilog for RTL Design. - Strong experience in designing IPs using AXI4, AXI4 Lite, and AXI4 Stream Protocols. - Comprehensive understanding of Xilinx FPGA architectures and proficiency in using tools like Vivado. - Solid knowledge of digital signal processing techniques, including Fast Fourier Transform, linear algebra, and complex algebra. - Experience in the realization of baseband processing for wireless systems, such as OFDM. - Proven ability to innovate and research unfamiliar technologies applicable to product development. - Strong organizational skills with the ability to manage projects, timelines, and cross-functional communication effectively. (Note: Benefits such as great career growth, ESOPs, Gratuity, PF, and Health Insurance are offered by the company.)