01Overview
Job Description
Could power, rather than compute, become the biggest hurdle for AI infrastructure A US-based AI chiplet startup believes the answer could shape the next generation of AI chips.
The company's modular chiplet architecture reflects a broader industry shift towards flexible, power-efficient AI processor design.
A US-based AI chiplet startup, TYLsemi, is tackling what it believes could become one of the biggest engineering challenges facing artificial intelligence hardware: efficient power delivery. As AI accelerators continue to demand more energy, the startup is developing modular chiplet technology designed to reduce the cost and complexity of custom AI chip development, improve scalability, and make power delivery a core part of processor design rather than a supporting function.
In an exclusive interaction, Mohit Gupta, Founder and CEO of TYLsemi, argues that while the industry remains focused on building faster AI processors, an equally important challenge is emerging. The biggest problem is power, he says, explaining that customers are increasingly constrained by the available power envelope rather than compute availability alone.
That shift is beginning to influence how AI silicon is designed. Instead of relying on monolithic architectures, modular chiplets allow functions such as compute, memory interfaces, I/O, and power delivery to be developed and optimised independently. The CEO believes this approach not only offers greater design flexibility but also addresses one of the key limitations of scaling AI infrastructure.
According to Mohit, improving power delivery could save around 300 to 500 watts on an AI accelerator consuming roughly 3kW. At hyperscale, he argues, those savings are less about reducing electricity bills than about enabling operators to deploy additional AI accelerators within the same power envelope, allowing more compute to be deployed using existing infrastructure.
Mohit Gupta, Founder and Chief Executive Officer, TYLsemi The conversation points to a broader shift in semiconductor engineering. As AI models grow larger and accelerator power requirements continue to climb, performance alone may no longer define the next generation of AI hardware. Packaging, power efficiency, and power delivery are becoming equally important design considerations.
Whether power ultimately becomes AI's defining hardware constraint remains to be seen. But if the assessment proves correct, the next leap in AI may depend not only on building more powerful chips, but also on delivering power to them more intelligently. The broader conversation also touches on how chiplets, custom silicon, and packaging are reshaping AI hardware. .
