01Overview
Senior Staff Formal Verification Engineer
We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D; capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
You have spent the better part of a decade proving that digital designs actually work, not just that they pass testbenches. Formal verification is where you live because you know that simulation can only show the presence of bugs, while formal methods can prove their absence. You have seen what happens when a corner case slips through, and you are the engineer who makes sure it does not.
You understand RTL at a level that lets you read a design and immediately spot the edge cases that will break it. Temporal logic is not abstract theory to you, it is the language you use to describe what correct behavior actually means. You have worked with tools like Jasper or VC-Formal enough to know their strengths, their quirks, and when to push back on a proof that looks complete but is not.
Mentoring comes naturally because you remember what it was like to debug your first failed assertion at 2am, and you would rather teach someone to set up a clean proof than fix their setup later. You can sit with a design team in Bangalore, walk through a formal verification plan, and leave them understanding not just what you are checking but why it matters.
What You'll Be Doing
Build and maintain an end-to-end formal verification flow that integrates cleanly into the broader verification process, not a standalone tool that lives in a corner
Create formal verification plans that identify the key behaviors worth proving, then develop the assertions, assumptions, and cover properties that actually close on tho .
