Staff/Senior Staff Engineer - AMS Verification

To work in AMS Verification domain with relevant experience in mixed signal SOCs or subsystems/IPs.Leading a project for AMS requirements is a value add.Proficiency in AMS simulation environment using Cadence/Synopsys/Mentor toolsKnowledge of digital design techniques, Verilog HDL, and standard RTL coding styles, as well as analog circuit basics, with previous analog design experience a plus.Candidate should be familiar with the concepts of behavioral modeling - both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS)Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plusFunctional knowledge of analog and mixed signal building blocks, such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expectedExperience working on AMS Verification on multiple SOCs or sub-systemsWorking knowledge of Perl / Skill/ Python/Tcl or other scripting relevant language is a plusCandidate should have ability to lead a project team, and work collaboratively in a multi-site development environmentDelivery oriented, Passionate to learn and explore, Transparent in communication, Flexibility related to project situationsCandidates should have a good knowledge of analog and mixed signal electronics, test-plan development, tools and flows.Develop and execute top-level test cases, self-checking test benches and regressions suitesDeveloping and validating high-performance behavior modelsVerifying of block-level and chip-level functionality and performanceTeam player with good communication skills and previous experience in delivering solutions for a multi-national clientTool suites : Predominantly analog (Cadence - Virtuoso). SPICE simulator experienceFluent with Cadence-based flow- Create schematics, Simulator/Netlist options etc.Ability to extract simulation results, capture in a document and present to the team for peer reviewSupporting silicon evaluation and comparing measurement results with simulationsUVM and assertion knowledge would be an advantageExperience Level: 10-15 years in Industry Education

Bachelor or Masters degree in Electrical and/or Computer Engineering Minimum Qualifications: Proficient in at least one of the following languages: Verilog, System Verilog, Verilog AMS.Strong understanding of analog circuits, digital design processes, and top-level integration.Basic knowledge of PMIC and DC-DC converters.Excellent simulation debugging skills, with the ability to analyze waveforms and identify issues in schematics, models, or RTL.Proficient in Unix environment and shell scripting, with a basic understanding of Python.Preferred Qualifications: Mentoring skillsExceptional problem-solving skillsGood written and oral communication skillsBenefits & Perks : Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun. Equity Rewards (RSUs)Employee Stock Purchase Plan (ESPP)Insurance plans with Outpatient coverNational Pension Scheme (NPS)Flexible work policyChildcare supportWe are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status. .